Japanese patent application no. 2002-35852 filed on Feb. 13, 2002, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor memory device having a nonvolatile memory cell controlled by a control gate.
A MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -substrate) type is known as one example of the nonvolatile semiconductor memory device. In this type, a gate insulating layer between a channel and a gate is constructed by a laminating layer body of a silicon oxide film, a silicon nitride film and a silicon oxide film, and electric charges are trapped in the silicon nitride film.
This MONOS type nonvolatile semiconductor memory device is disclosed in a publication: Y. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers, p. 122 -p. 123. In this publication, a MONOS flash memory cell having two nonvolatile memory cells (also called MONOS memory elements or cells) controlled by one word gate and two control gates is disclosed. Namely, one flash memory cell has two trap sites of the electric charges.
A memory cell array region is constructed by arranging a plurality of MONOS flash memory cells having such a structure in row and column directions.
Two bit lines, one word line and two control gate lines are required to operate this MONOS flash memory cell. In this case, when many memory cells are operated, these lines can be commonly connected when the same potential is set even in a different control gate.
There are erasion, a program and reading of data in the operation of the flash memory of this kind. The program and the reading of data are normally simultaneously executed by a selection cell (selected nonvolatile memory cell) of 8 bits or 16 bits.
Here, in the MONOS flash memory, a plurality of MONOS flash memory cells not separated in elements from each other are connected to one word line. When the read or the program of data is executed with respect to a certain specific selection cell, the voltage of the MONOS flash memory having this selection cell must be set and the voltage of a MONOS flash memory cell adjacent to this MONOS flash memory must be also suitably set.
For example, a case in which one of the memory cells is a selection cell and the other is a non-selection cell (called an opposite cell), will be considered. When data are read from the selection cell, a selection voltage is supplied to the control gate of the selection cell, and an override voltage is supplied to the control gate of the opposite cell, and 0 V is supplied to the control gate of the non-selection cell except for the opposite cell. These voltages are similarly supplied when data is programmed except that the values of the selection voltage and the override voltage at the data program time are merely different from those at the data read time.
Here, the override voltage is a voltage required to flow a read current or a program current by turning-on a transistor of the opposite cell irrespective of the existence or nonexistence of the program of the opposite cell.
Here, the override voltage at the data read time, and the selection voltage and the override voltage at the data program time are higher than a power supply voltage, and are supplied from a booster circuit.
In the nonvolatile semiconductor memory device of this kind, it is particularly necessary to perform a read operation at high speed. However, it took time to raise the voltage of the control gate line from 0 V to a final voltage.
Therefore, the present invention may provide a nonvolatile semiconductor memory device able to shorten a time for raising the control gate voltage until the final voltage.
The present invention may further provide a nonvolatile semiconductor memory device able to reduce a consumed current while the raising time of the control voltage is shortened.
A nonvolatile semiconductor memory device according to the present invention includes: a memory cell array region in which a plurality of nonvolatile memory cells are arranged, each of the nonvolatile memory cells including a control gate; and a control gate voltage generation section which generates a voltage driving the control gate of each of the nonvolatile memory cells in the memory cell array region. The control gate voltage generation section includes: a booster circuit which generates a plurality of voltages; and a voltage control circuit which includes a plurality of voltage output terminals, the voltage control circuit switching and outputting the voltages from the booster circuit to the voltage output terminals in accordance with a selection state of the nonvolatile memory cells. The voltage control circuit outputs a maximum voltage among the voltages to the voltage output terminals commonly during a pre-drive period which is a period before the voltages are outputted from the voltage output terminals.
In accordance with the present invention, the maximum voltage among the final voltages is supplied to the control gate during the pre-drive period irrespective of the magnitude of the final voltage set by a control gate driver, and the maximum voltage is pre-driven. Thus, the current driving abilities of the control gate drivers while driving can be set to be approximately equal to each other. Accordingly, it is possible to shorten a period for raising the control gate voltage until the final voltage.
The nonvolatile semiconductor memory device of the present invention may further include a plurality of control gate drivers, each of the control gate drivers including a CMOS transistor which selects one voltage between one of the voltages from the voltage control circuit and a voltage equal to or lower than a ground voltage, and supplies the selected voltage to the control gate. Each CMOS transistor in these plurality of control gate drivers may be switched in accordance with a change of a memory address. The voltage control circuit may set the pre-drive period after a switching period of the CMOS transistor has passed.
In the switching period of the CMOS transistor, a through current flows in the CMOS transistor. When the pre-drive period is set in this switching period, the maximum voltage is supplied from the booster circuit to the CMOS transistor. Accordingly, the voltage of the booster circuit drops by the through current.
The voltage control circuit may set the pre-drive period over a predetermined period based on an address transition signal which changes at a transition time of the memory address in order to set the pre-drive period by avoiding the switching period of the CMOS transistor.
In the above feature, the voltage control circuit may have first and second voltage input terminals and first and second voltage output terminals, and may control switching of a connection state between the first and second voltage input terminals and the first and second voltage output terminals in accordance with the selection state of the nonvolatile memory, cells.
In this feature, in the voltage control circuit, a first control gate selection voltage may be inputted to the first voltage input terminal and a first override voltage higher than the first control gate selection voltage may be inputted to the second voltage input terminal when data is read, and the first override voltage (maximum voltage) may be outputted from the first and second voltage output terminals during the pre-drive period.
Further, in the voltage control circuit, a second control gate selection voltage maybe inputted to the first voltage input terminal and a second override voltage higher than the second control gate selection voltage may be inputted to the second voltage input terminal when data is programmed, and the second override (maximum voltage) voltage may be outputted from the first and second voltage output terminals during the pre-drive period.
In this feature, the voltage control circuit may be set to a disconnection state, in which no voltage is outputted from the booster circuit to both of the first and second voltage output terminals, in a period including the switching period of the CMOS transistor.
Further, the voltage control circuit may output a power supply voltage to the first and second voltage output terminals in the period including the switching period of the CMOS transistor.
As mentioned above, the through current flows in the switching period of the CMOS transistor. Accordingly, the voltage drop in the booster circuit can be prevented by disconnecting the booster circuit from the voltage control circuit during this period. Further, the switching operation of the CMOS transistor can be realized by using the power supply voltage without using the voltage of the booster circuit.
The present invention may be applied to a nonvolatile semiconductor memory device in which memory cells are arranged in a row direction and a column direction in the memory cell array region, each of the memory cells having one word gate, and first and second nonvolatile memory cells controlled by first and second control gates. The nonvolatile semiconductor memory device having a memory cell structure except for the memory cell may be also used.
Each of the first and second nonvolatile memory cells constituting the memory cell may have an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O) as a trap site of electric charges. In addition, other types of trap structure can be adopted.